The quest to develop larger and larger semiconductors of the dynamic random access memory (DRAM) type is a well-known goal. The industry has steadly progressed from DRAMs of the 16K type, shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, and the 64K type, shown in U.S. Pat. No. 4,055,444 issued to Rao, to DRAMS of the 1 Megabit type, as described in U.S. Pat. No. 4,658,377 issued to McElroy. DRAMs of the 4 Megabit type are now being produced. Production plans for 16 Megabit DRAMs constructed of submicron technology now exist and experimentation of 64 Megabit DRAMs has begun. One factor furthering the development of larger DRAMs is the reduction in memory cell geometries as illustrated in U.S. Pat. No. 4,240,092 to Kuo (a planar capacitor cell), and as illustrated in U.S. Pat. No. 4,721,987 to Baglee et al. (a trench capacitor cell).
In semiconductor chip fabrication, engineers routinely analyze defective chips to discover the cause of defects, thereby hoping to prevent future ones. This process is commonly referred to as "Failure Analysis" in the semiconductor industry. TEM (Transmission Electron Microscopy) and SEM (Scanning Electron Microscopy) photographs are illustrative of two techniques engineers utilize in solving defects. Engineers view these photographs to find defects such as metal shorts, capacitor holes, particle failures, and others.
The packing of more and more memory cells of smaller geometries on a single semiconductor chip in the fabrication of larger and larger DRAMs complicates failure analysis. Defects are harder to determine because they are harder to physically locate and view.
It is an object therefore of this invention to provide a technique to analyze defects in semiconductor chips and particularly in DRAMs.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.